1. Field of the Invention
The present invention generally relates to a multi-processor system, and particularly to a multi-processor system using a plurality of processors which are connected via a data bus for executing non-synchronous (or asynchronous) operations.
2. Description of the Prior Art
FIG. 7 is a schematic block diagram showing an arrangement of a conventional multi-processor system for executing a non-synchronous operation.
As shown in FIG. 7, the multi-processor system 100 includes a plurality of processors CPU1 to CPUn each of which executes a non-synchronous operation. The processors CPU1 to CPUn have local memory modules (or memory modules) LOCAL1 to LOCALn respectively dedicated thereto (here, “n” being a natural number as n>1). These processors CPU1 to CPUn are connected via communication memory modules (or memory modules) COMM1 to COMMn respectively to a common data bus 101 including such as a data switching unit. In this conventional example, a data communication bus is used as the data bus 101.
For carrying out a non-synchronous operation, necessary data and commands are previously stored in the local memory modules LOCAL1 to LOCALn, which are scheduled by a compiler with consideration of a delay caused in operating a data switching unit. Thus, when any of the processors accesses a communication memory, the data stored in the communication memory must be always made valid for permitting the non-synchronous execution.
However, the conventional system can perform the non-synchronous operation only when each of the local memory modules LCOAL1 to LOCALn for high-speed operation contains all the necessary data and commands for accessing. This requires each of the local memory modules LOCAL1 to LOCALn to have considerably a large storage capacity. Also, in the case where cache memory modules are used for generally increasing the operation speed thereof, there may occur an uncertainty in operation time of the processors when a miss hit of a cache is detected. As a result, the multi-processor system can hardly execute the non-synchronous operation.
It is noted here that, in this description, the terminology “hit” or “miss hit” of a cache is used to mean that there exists data or no data to be accessed in a cache memory, respectively.